? semiconductor components industries, llc, 2003 july, 2003 ? rev. p1 1 publication order number: emd5dxv6/d EMD5DXV6T1, emd5dxv6t5 preferred devices product preview dual bias resistor transistors npn and pnp silicon surface mount transistors with monolithic bias resistor network the brt (bias resistor transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base?emitter resistor. these digital transistors are designed to replace a single device and its external resistor bias network. the brt eliminates these individual components by integrating them into a single device. in the EMD5DXV6T1 series, two complementary brt devices are housed in the sot?563 package which is ideal for low power surface mount applications where board space is at a premium. ? simplifies circuit design ? reduces board space ? reduces component count ? available in 8 mm, 7 inch tape and reel ? lead free solder plating this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. preferred devices are recommended choices for future use and best overall value. q 1 r 1 r 2 r 2 r 1 q 2 (1) (2) (3) (4) (5) (6) http://onsemi.com sot?563 case 463a plastic 1 2 3 6 5 4 u5 = specific device code d = date code marking diagram u5 d device package shipping ordering information EMD5DXV6T1 sot?563 4 mm pitch 4000/tape & reel emd5dxv6t5 sot?563 2 mm pitch 8000/tape & reel
EMD5DXV6T1, emd5dxv6t5 http://onsemi.com 2 maximum ratings (t a = 25 c unless otherwise noted, common for q 1 and q 2 , ? minus sign for q 1 (pnp) omitted) rating symbol value unit collector-base voltage v cbo 50 vdc collector-emitter voltage v ceo 50 vdc collector current i c 100 madc thermal characteristics characteristic (one junction heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 357 (note 1) 2.9 (note 1) mw mw/ c thermal resistance junction-to-ambient r ja 350 (note 1) c/w characteristic (both junctions heated) symbol max unit total device dissipation t a = 25 c derate above 25 c p d 500 (note 1) 4.0 (note 1) mw mw/ c thermal resistance junction-to-ambient r ja 250 (note 1) c/w junction and storage temperature t j , t stg ?55 to +150 c 1. fr?4 @ minimum pad
EMD5DXV6T1, emd5dxv6t5 http://onsemi.com 3 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit q1 transistor: pnp off characteristics collector-base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector-emitter cutoff current (v cb = 50 v, i b = 0) i ceo ? ? 500 nadc emitter-base cutoff current (v eb = 6.0, i c = 5.0 ma) i ebo ? ? 1.0 madc on characteristics collector-base breakdown voltage (i c = 10 a, i e = 0) v (br)cbo 50 ? ? vdc collector-emitter breakdown voltage (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc dc current gain (v ce = 10 v, i c = 5.0 ma) h fe 20 35 ? collector?emitter saturation voltage (i c = 10 ma, i b = 0.3 ma) v ce(sat) ? ? 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor r1 3.3 4.7 6.1 k resistor ratio r1/r2 0.38 0.47 0.56 q2 transistor: npn off characteristics collector-base cutoff current (v cb = 50 v, i e = 0) i cbo ? ? 100 nadc collector-emitter cutoff current (v cb = 50 v, i b = 0) i ceo ? ? 500 nadc emitter-base cutoff current (v eb = 6.0, i c = 5.0 ma) i ebo ? ? 0.1 madc on characteristics collector-base breakdown voltage (i c = 10 a, i e = 0) v (br)cbo 50 ? ? vdc collector-emitter breakdown voltage (i c = 2.0 ma, i b = 0) v (br)ceo 50 ? ? vdc dc current gain (v ce = 10 v, i c = 5.0 ma) h fe 80 140 ? collector?emitter saturation voltage (i c = 10 ma, i b = 0.3 ma) v ce(sat) ? ? 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k ) v ol ? ? 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k ) v oh 4.9 ? ? vdc input resistor r1 33 47 61 k resistor ratio r1/r2 0.8 1.0 1.2
EMD5DXV6T1, emd5dxv6t5 http://onsemi.com 4 figure 1. derating curve 250 200 150 100 50 0 -50 0 50 100 150 t a , ambient temperature ( c) p d , power dissipation (milliwatts) r ja = 833 c/w
EMD5DXV6T1, emd5dxv6t5 http://onsemi.com 5 typical electrical characteristics e EMD5DXV6T1 pnp transistor 25 c i c , collector current (ma) h fe , dc current gain figure 2. v ce(sat) versus i c figure 3. dc current gain figure 4. output capacitance figure 5. output current versus input voltage 1000 10 i c , collector current (ma) t a =75 c 25 c -25 c 100 1 1 1000 75 c 25 c 100 0 v in , input voltage (volts) 10 1 0.1 0.01 2468 12 t a =-25 c v ce(sat) , maximum collector voltage (volts) t a =75 c -25 c 0.01 0.1 1 40 i c , collector current (ma) 0 20 50 010203040 12 6 4 2 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) i c /i b = 10 v ce = 10 v f = 1 mhz i e = 0 ma t a = 25 c v o = 5 v 30 10 60 100 10 10 8 15 25 35 45 5 series 1 10
EMD5DXV6T1, emd5dxv6t5 http://onsemi.com 6 typical electrical characteristics e EMD5DXV6T1 npn transistor v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain figure 6. v ce(sat) versus i c 0246810 100 10 1 0.1 0.01 0.001 v in , input voltage (volts) t a =-25 c 75 c 25 c figure 7. dc current gain figure 8. output capacitance 100 10 1 0.1 010 203040 50 i c , collector current (ma) figure 9. output current versus input voltage 1000 10 i c , collector current (ma) t a =75 c 25 c -25 c 100 10 1 100 25 c 75 c 50 010203040 1 0.8 0.6 0.4 0.2 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) figure 10. input voltage versus output current 0 20 40 50 10 1 0.1 0.01 i c , collector current (ma) 25 c 75 c v ce(sat) , maximum collector voltage (volts) v ce = 10 v f = 1 mhz i e = 0 ma t a = 25 c v o = 5 v v o = 0.2 v i c /i b = 10 t a =-25 c t a =-25 c
EMD5DXV6T1, emd5dxv6t5 http://onsemi.com 7 the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 150 milliwatts. information for using the sot?563 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the to- tal design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. with the cor- rect pad geometry, the packages will self align when sub- jected to a solder reflow process. sot?563 power dissipation p d = t j(max) ? t a r ja p d = 150 c ? 25 c 833 c/w = 150 milliwatts the power dissipation of the sot?563 is a function of the pad size. this can vary from the minimum pad size for soldering to a pad size given for maximum power dissipa- tion. power dissipation for a surface mount device is deter- mined by t j(max) , the maximum rated junction temperature of the die, r ja , the thermal resistance from the device junction to ambient, and the operating temperature, t a . us- ing the values provided on the data sheet for the sot?563 package, p d can be calculated as follows: the 833 c/w for the sot?563 package assumes the use of the recommended footprint on a glass epoxy printed cir- cuit board to achieve a power dissipation of 150 milliwatts. there are other alternatives to achieving higher power dis- sipation from the sot?563 package. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, an aluminum core board, the power dis- sipation can be doubled using the same footprint. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. there- fore, the following items should always be observed in or- der to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and solder- ing should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum tem- perature ratings as shown on the data sheet. when using infrared heating with the reflow soldering meth- od, the difference shall be a maximum of 10 c. ? the soldering temperature and time shall not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maxi- mum temperature gradient shall be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied dur- ing cooling. * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device. 1.35 0.0531 0.5 0.0197 mm inches scale 20:1 0.5 0.0197 1.0 0.0394 0.45 0.0177 0.3 0.0118 sot?563
EMD5DXV6T1, emd5dxv6t5 http://onsemi.com 8 package dimensions sot?563, 6 lead case 463a?01 issue o g m 0.08 (0.003) x d 6 5 pl c j ?x? ?y? notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeters 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. dim a min max min max inches 1.50 1.70 0.059 0.067 millimeters b 1.10 1.30 0.043 0.051 c 0.50 0.60 0.020 0.024 d 0.17 0.27 0.007 0.011 g 0.50 bsc 0.020 bsc j 0.08 0.18 0.003 0.007 k s style 1: pin 1. emitter 1 2. base 1 3. collector 2 4. emitter 2 5. base 2 6. collector 1 a b y 12 3 4 5 s k style 2: pin 1. emitter 1 2. emitter2 3. base 2 4. collector 2 5. base 1 6. collector 1 0.004 0.012 0.059 0.067 0.10 0.30 1.50 1.70 6 style 3: pin 1. cathode 1 2. cathode 1 3. anode/anode 2 4. cathode 2 5. cathode 2 6. anode/anode 1 style 4: pin 1. collector 2. collector 3. base 4. emitter 5. collector 6. collector on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 2?9?1 kamimeguro, meguro?ku, tokyo, japan 153?0051 phone : 81?3?5773?3850 on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. emd5dxv6/d thermal clad is a trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800?282?9855 toll free usa/canada
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